Hitotsu said:
Thank you so much for telling me that. May I ask how do i simulate fs & sf? I do know for ff is just 'fast'
fs means
fast pfets combined with
slow nfets,
sf the other way round (and I guess it's clear what
ff means ;-) ). These are other possible "worst case" combinations which could occur on a processed wafer. If your PDK contains these models, it is wise to simulate with them.
Hitotsu said:
I don't really get the MC-mixed condition, whats is that and how can i simulate it? pls advice.
I did simulate the worst case (temp, vdd & res) though
The problem with oscillators sometimes is, that they won't self-start under special condition combinations, somewhere in the 3-dimensional PVT space, which cannot be found by just simulating the extreme corners of this space (I once happened to have an oscillator design, which worked (self-started) at all simulated PVT
corner conditions, but refused to do so at the condition combination {fs , highest (!) VDD, in the T-range -25 .. 0°C}. This was discovered during lab experiments on delivered chips, and could be verified by postLayout simulation under appropriately combined simulation conditions).
This is what I meant with
MC-mixed conditions: A selection of different PVT simulation combinations
apart from the corner conditions. Not necessarily selected by a Monte Carlo mechanism (actually I don't know if it is possible to select random PVT combinations by the MC method); such local PVT points (combinations) could also be selected intuitively.
If you have the time, just try some more points in the PVT space! With slowly ramping-up VDD.
Good luck! erikl