What to take care of when doing floorplan?

[neal]

floorplan

Hi everyone,
when we do floorplan, There are so many things we should take care, especially for SOC design. But who can collect the information as many as possible into one file . I think that is very usesul for digital enginner. Can you post what you know about the FP .

 

[sunjimmy]

Re: floorplan

Hi,

The principle behind SOC floorplan is to prevent the interference between different blocks ,especially the analog blocks. So how to reduce the noise
on chip is the primary issue. Here are two useful articles for your reference .

Hope it helps : )

 

[neal]

Re: floorplan

yes ,hehe. 3x.
But when we do full chip floorplan ,we should consider the congestion, the noise between the analog module and digital module, chipsize , power, performance. We should do it according to the specification.
How to minmize the congestion problem when we want to get a better performance ? we may use EDA tools .But for floorpan, there are still many thing we should do mannully.
During the curse of mannul work, I think the problem what we should take care is even important. Can you show us in detail?