latch
To the new designer, latch is always a problem in synthesis. Check your verilog code. If you have a combinational always block which has one condition branch, you will get latch in the synthesis.
always @(a or b)
begin
if (a)
out = b;
// no else here will give a latch
end
So you can check your verilog code, and add a else condition for combinational blocks.
But experienced designer can use latch to reduce the design area. and get low power as well.
Latch is tough component in the design. It can give difficulty in DFT, timing and design. But it can save area and power.
MAGIC!!