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What should I consider when doing synthesis and timing analysis for design with latch

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lizeer

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hi,
I'm using latch in my design. what should I consider when doing synthesis and timing analysis for my design?
 

stay_in_chaos

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Re: latch

why can,t you use latch only during ur synthesis.
or u can change the design
 

lizeer

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Re: latch

If in my design have both latch and flip-flop, what should I do?
 

tigerajs

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Re: latch

latch is not very good, you can change u design
 

nand_gates

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Re: latch

You can use latches in ur design but this will complicate ur job
for timing analysis and DFT.
 

lizeer

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Re: latch

I am very new in asic design,
can you explain how latch can effect timing analysis and dft?
thank you..
 

eda_wiz

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latch

Unlike FF Latch has no equivalent scan cell. So you cannot insert full scan during DFT if you se a latch.
Timing analysis can be done but is difficult than only FF design, as usually synthesis tools do "Time Borrowing" around latches.

check this page if u dont know time borrowing
https://www.synopsys.com/products/logic/design_comp_tb.html
 

leonlin520

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Re: latch

edge triggered or level signal
 

jjww110

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latch

you should not use latch , some company prohibit in design rule!!
 

zhustudio

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latch

To the new designer, latch is always a problem in synthesis. Check your verilog code. If you have a combinational always block which has one condition branch, you will get latch in the synthesis.

always @(a or b)
begin
if (a)
out = b;
// no else here will give a latch
end

So you can check your verilog code, and add a else condition for combinational blocks.

But experienced designer can use latch to reduce the design area. and get low power as well.

Latch is tough component in the design. It can give difficulty in DFT, timing and design. But it can save area and power.

MAGIC!!
 

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