Jul 8, 2007 #1 ryusgnal Advanced Member level 4 Joined Oct 4, 2005 Messages 102 Helped 3 Reputation 6 Reaction score 1 Trophy points 1,298 Location Malaysia Activity points 1,992 Can anybody provide me the circuit that can perform the timing below? **broken link removed**
Jul 8, 2007 #2 lordsathish Full Member level 5 Joined Feb 11, 2006 Messages 246 Helped 33 Reputation 66 Reaction score 3 Trophy points 1,298 Location Asia Activity points 2,698 Re: Circuit design you check out this link... its about this cloc multiplier...
Jul 8, 2007 #3 S sekapr Advanced Member level 4 Joined Jul 27, 2006 Messages 100 Helped 9 Reputation 18 Reaction score 4 Trophy points 1,298 Activity points 1,680 Re: Circuit design This is a simple clock divider. In a D FF connect Q-bar to D input.
Jul 10, 2007 #4 deh_fuhrer Full Member level 5 Joined Jul 25, 2006 Messages 276 Helped 46 Reputation 92 Reaction score 18 Trophy points 1,298 Activity points 2,862 Re: Circuit design its a clock multiplier...consult fsm design concepts.... Added after 5 minutes: i think this circuit can be design using asynchronous fsm design techniques...
Re: Circuit design its a clock multiplier...consult fsm design concepts.... Added after 5 minutes: i think this circuit can be design using asynchronous fsm design techniques...
Jul 11, 2007 #5 P phoenixfeng Full Member level 2 Joined Mar 27, 2004 Messages 147 Helped 15 Reputation 30 Reaction score 6 Trophy points 1,298 Activity points 770 Circuit design u should avoid using the clock generated from other signal in synchronous design
Jul 23, 2007 #6 S sunil_ic Newbie level 4 Joined May 22, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,325 Circuit design try exor gate where one input is clock and another is feedback from output with some delay. use buffer or even number inverters. Added after 49 seconds: for delay, use buffers or even number of inverters
Circuit design try exor gate where one input is clock and another is feedback from output with some delay. use buffer or even number inverters. Added after 49 seconds: for delay, use buffers or even number of inverters