Sorry for reply so lately. I can not log in today, it is strange
Vdd=1.8, single suply. process: 0.18um.
Vin is from 0~Vdd, single ended.
Clock 1MHz. Resolution:8bit, effective bit >7bit
the power consumption should be less than 6mW.
Reference: internal, (from bandgap and it is also needed to be designed bymyself)
The package and control type is not clear up to now.
Is SAR the best choice?
If using pipleline, is it possible?(I mean the power consumption)
Does the single ended to differential circuit needed in pipeline?
and the range of Vin is also a problem, it is from 0~Vdd, is it OK for pipeline?
thanks a lot.
Added after 1 minutes:
If high freq clock is not available, which ADC should I choose?