What kind of ADC should I choose?

[benchen]

The resolution is 8bit, Clock Freq is about 1MHz.
Which structure should I choose to realize low power consumption and small area?
Thanks a lot.

 

[mists]

I think SAR ADC is suitable!

 

[eezou]

Flash ADC

 

[polymath]

Hi benchen

Is the 1MHz a clock that you system has available or did you mean you want 1Msps?

A res. of 8bit - OK, but what accuracy? ±0.5Lsb? ±1Lsb? ± 2Lsb? .....

Low power - how low?
Input voltage range?
Input number & type single/double ended?
What type of output serial/parallel?
What supply voltage? single rail/double rail?
What reference - internal/external?
What control - command/autorun?
What package - dip/smt

better definition => better solution

... Polymath

 

[ericliu]

I think the two-step subranging arhitecture is good.

 

[pfd001]

SAR is the best choice if the high frequency clock is already available

 

[cinvo]

Charge Redistribution SAR ADC

 

[zenisle]

sigma-delta or sar adc

 

[manissri]

hi sar adc will be good ..

 

[polymath]

Hi All
How can any of you sincerely recommend any type of ADC WITHOUT knowing the application or requirement? - or do you post to confuse?

The UNKNOWING-SEEING-BLIND LEADING THE IGNORANT-BLIND.

Is it little wonder there are so many confused readers on EDAboard.

... Polymath

 

[sankudey]

along with the question of polymath...I want to add one more...which i think is importatnt one....

what is the technology and technology node......

BTW: why the question originator is silent for so long


sankudey

 

[benchen]

Sorry for reply so lately. I can not log in today, it is strange

Vdd=1.8, single suply. process: 0.18um.
Vin is from 0~Vdd, single ended.
Clock 1MHz. Resolution:8bit, effective bit >7bit
the power consumption should be less than 6mW.
Reference: internal, (from bandgap and it is also needed to be designed bymyself)
The package and control type is not clear up to now.

Is SAR the best choice?

If using pipleline, is it possible?(I mean the power consumption)
Does the single ended to differential circuit needed in pipeline?
and the range of Vin is also a problem, it is from 0~Vdd, is it OK for pipeline?

thanks a lot.

Added after 1 minutes:

If high freq clock is not available, which ADC should I choose?

 

[asping]

Is 6mw the total power of ADC and bandgap ?

 

[benchen]

do not include bandgap. Is it possible? It sounds too hard.

 

[sankudey]

Hi,
I guess ur spec of 6mW power consumption halted the discussion for a long.....

I just can say one thing from my experiance.....u should avoid to chose a architecture who potentially requires S/H or T/H circuits...because...in CMOS.....as generally closed loop architecture is followed (other than like HBT/BJT...where openloop is preffered for higher frequency).....an OP-AMP comes as mandatory......and it is highly possible that one S/H or T/H pursuing 8(+) bit of resolution ... may consume a potential part of 6mW.....I told 8-bit as for higher accuracy u may have to employ boot-strapping etc....ultimately increasing transistor count......


u keep on updating on this issue....it seems to be a real challenge.....

gd luck...

sankudey