[SOLVED] what is wrong with this code?? (Verilog)

[surajdash]

always @(posedge idclk)
begin
if((!carry)&&(!borrow))
toggle = @ (negedge idclk)~ toggle;
end

the error while synthesize xst is:

ERROR:Xst:896 - "adpll.v" line 151: Unsupported Event Control.

dire need of help...

 

[FvM]

Re: what is wrong with this code??

You can't use nested edge sensitive conditions (at least in Verilog for synthesis).

 

[surajdash]

Re: what is wrong with this code??

is thr any alternative to such code??

 

[Fl1pFl0p]

Re: what is wrong with this code??

this line looks wrong.

toggle = @ (negedge idclk)~ toggle;

@(negedge idclk) is an event. Remove this part. so you have:

toggle = ~toggle;

 

[surajdash]

Re: what is wrong with this code??

but what if i want that statement to execute only at the negative edge of the clk??
how do i achieve that??

 

[FvM]

Re: what is wrong with this code??

but what if i want that statement to execute only at the negative edge of the clk??
how do i achieve that??

The always block as a whole will be only "executed" at the rising edge of idclk. So even if the construct would be accepted for synthesis, the code is completely useless.

Please reconsider what you want to achieve.

 

[surajdash]

Re: what is wrong with this code??

actually what i want to acieve is a very big code i was just giving an example.. the same error also happens when i write..

always
begin
toggle @(posedge clk) = ~toggle;
end

 

[FvM]

Re: what is wrong with this code??

toggle @(posedge clk) = ~toggle

assignments with event control aren't supported by any synthesis tool I'm aware of. You have to translate them to edge sensitive always blocks.

 

[surajdash]

Re: what is wrong with this code??

can u plz site me an example to do so??

m pasting my code if that might b of ne help for u to understand my problem

always
begin
if ((!carry)&&(!borrow)&&(!cond[2])&&(!cond[3])&&(!cond[4])&&(!cond[5]))
begin
cond[1] = `high;
@(posedge idclk) toggle = ~toggle;
#(idclk_p) cond[1] = `low;
end
else if ((!toggle)&&(carry)&&(!cond[1])&&(!cond[3])&&(!cond[4])&&(!cond[5]))
begin
cond[2] = `high;
@(posedge idclk) toggle = `high;
#(idclk_p) toggle = `low;
#(2*idclk_p) cond[2] = `low;
end
else if ((toggle)&&(carry)&&(!cond[1])&&(!cond[2])&&(!cond[4])&&(!cond[5]))
begin
cond[3] = `high;
@(posedge idclk) toggle = `low;
#(2*idclk_p) cond[3]= `low;
end
else if ((toggle)&&(borrow)&&(!cond[1])&&(!cond[2])&&(!cond[3])&&(!cond[5]))
begin
cond[4] = `high;
@(posedge idclk) toggle = `low;
#(idclk_p) toggle = `high;
#(2*idclk_p) cond[4] = `low;
end
else if ((!toggle)&&(borrow)&&(!cond[1])&&(!cond[2])&&(!cond[3])&&(!cond[4]))
begin
cond[5] = `high;
@(posedge idclk) toggle = `high;
#(2*idclk_p) cond[5] = `low;
end
end

 

[FvM]

Re: what is wrong with this code??

Looking at the latest code, the problem turns out even worse. While the @(posedge xx) event control can be implemented in synthesis by reordering the code, you also have #xx timing control expressions that aren't synthesizable at all. You need to study the basics of Verilog for hardware design and rewrite the code from the scratch - if you intend to synthesize it.

 

[surajdash]

Re: what is wrong with this code??

Looking at the latest code, the problem turns out even worse. While the @(posedge xx) event control can be implemented in synthesis by reordering the code, you also have #xx timing control expressions that aren't synthesizable at all. You need to study the basics of Verilog for hardware design and rewrite the code from the scratch - if you intend to synthesize it.

the # (idclk_p) is synthesizable they r just integer values calculate as the time period of idclk.
the problem lies only wid the @(posedge idclk)

n all i wanna know wats its alternative.. if u cn plz just temme the source frm whr i cn read abt it...
plz i need some help..

 

[FvM]

Re: what is wrong with this code??

the # (idclk_p) is synthesizable they r just integer values calculate as the time period of idclk.

Where did you get this idea? In fact, # timing control statements are ignored by the synthesis tool, but the code won't work as intended.

 

[surajdash]

Re: what is wrong with this code??

okay so plz cn u temme a logic to simulate a increment decrement counter dco...
the code was for that only.. it wud be of great help i m attaching a pdf for this logic...

 

[lucbra]

Re: what is wrong with this code??

You need to study the basics of Verilog for hardware design and rewrite the code from the scratch - if you intend to synthesize it.

FvM states correctly: if you intend to synthesize it.

Looking at your document, the algorithm is pseudo Verilog. You will need to translate to something that can be implemented in an FPGA. What you wrote is definitely not a good translation.

 

[surajdash]

Re: what is wrong with this code??

okay can someone plz help me ...
i just need to know how to create a delay that can be synthesized and not not ignored for synthesis...

 

[FvM]

Re: what is wrong with this code??

The logic shown in the adpll attachment is pure synchronously, every action takes place on the rising clock edge. It's obvious Verilog representation has all logic assignments placed in a clock synchronous always block. No additional timing or event control is needed then.

always @(posedge idclk)
begin
....
end

 

[vipinlal]

Re: what is wrong with this code??

one way is to create a state machine kind of thing. Whenever you want to wait for some time go to a particular state, where a counter will keep counting up until it reaches a particular value. The more high this value is the more the delay will be. After reaching this highest value reset the counter, and go to the state where you want to do the calculations.. and so on..

 

[surajdash]

Re: what is wrong with this code??

okay.. so the delay created by # xx is only for simulations??
it wont be synthesized but will it work nice for simulations.. i mean by seeing the result in xilinx after running the program by a testbench??

 

[surajdash]

Re: what is wrong with this code??

guys.. thank you all for ur responses.. i hv changed my code now...
hopefully this works .. hv some odr parts to cmplete too.. this one yet goes like this...


always @(posedge idclk)
begin
if(!carry) c_check = `low;
if(!borrow) b_check = `low;
if (delay)
begin
d_counter = d_counter-1;
if (d_counter == 0)
delay = `low;
end
else if(c2_delay)
begin
toggle = `low;
delay = `high;
d_counter = 2;
c2_delay = `low;
end
else if(c4_delay)
begin
toggle = `high;
delay = `high;
d_counter = 2;
c4_delay = `low;
end
else if (c1)
toggle = ~toggle;
else if (c2)
begin
toggle = `high;
c_check = `high;
delay = `high;
d_counter = 1;
c2_delay = `high;
end
else if (c3)
begin
c_check = `high;
toggle = `low;
delay = `high;
d_counter = 2;
end
else if(c4)
begin
b_check = `high;
toggle = `low;
delay = `high;
d_counter = 1;
c4_delay = `high;
end
else if(c5)
begin
b_check = `high;
toggle = `high;
delay = `high;
d_counter = 2;
end
end

---------- Post added at 00:49 ---------- Previous post was at 00:46 ----------

hopefully its ok this time.. isnt it??

Don't use SMS typing, write complete words. Consider this a warning [alexan_e]

 

[FvM]

Re: what is wrong with this code??

At least, it looks like synthesizable Verilog now.

The code seems to represent a state machine, I wonder if the "if ... if else ..." spaghetti code can be better implemented by a case structure and a vectorial state variable. Another question is, if you intentionally use blocking assignments throughout the code. The general suggestion is to use non-blocking <= assignments for sequential code.

What's the purpose of the macros `low and `high in place of simple integer 0 and 1 respectively sized 1'b0 and 1'b1 constants?