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What is wrong with my simple code?

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Your COUNT register is uninitialized, so it defaults to 'x'.

If you are using Verilog 2001, try changing this:
reg [15:0] COUNT;
to this:
reg [15:0] COUNT = 0;

Or use an 'initial' statement to initialize COUNT to zero. That works in older Verilog.
 

Yes off Course .... there is no problem with code

EXCEPT Inilization of COUNT
 

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