what is useful skew in SoC Encounter?

[steven852]

What is the "useful skew" in SoC Encounter and how to use it? Is it part of an ECO process?

Thanks

 

[neo_chip]

useful skew is used to elimnate setup violations............
That is by adding delay in the clock path, the capturing edge is delayed. Therefore we have more time to capture the data, thus eliminating setup violations.....

 

[steven852]

If the capturing edge is delayed, the hold time would be in danger, right?

I found some material on the useful skew topic. Not having time to read them yet but it is nice to have some discussion.

Thanks

 

[rajesh9999]

True. It does effect hold times. However hold times voilations are easier to correct. All you need is add delay elements to the fastest path. Many times they get added naturally, like wire delays, coupling/fringe capacitance etc. after routing. If there are still hold voilations after routing, the tool can easily add buffers to the path to take care of hold voilations.

setup times are difficult to correct, so the trade-off will be worth it, especially in high speed designs.

 

[steven852]

Ok, that reasoning of setup/hold balancing makes more sense. An extended question on a current project (>500MHz): how do I justify when I should use "useful skew"? Without using it, I had a small violation on both setup and hold (less than 20ps). If using "useful skew", they were all removed. I don't know how SoC Encounter did that. Also since the violations were small, so the timing constraints might be over-constrainted too much. Thus, without using useful skew but modified a bit the timing constraints, the violations could be solved. But how what are the differences on these two approaches?

By the way, any application-wise information on the "useful skew"?

Thanks.

 

[funster]

sometime, the skew is usefule, thus you can borrow some time from successive

clock cycle.

best regards

What is the "useful skew" in SoC Encounter and how to use it? Is it part of an ECO process?

Thanks