The SPI has 3 lines:
MOSI - master out, slave in
MISO - master in, slave out
SCK - slave clock
Also there may be a slave select SS line, that activates the SPI interface on the slave.
Basicaly, both master and the slave have a shift register so that the data circulates between them through MOSI and MISO lines. Master generates the clock for transmission, with SCK.
Ussualy, an ADC is a slave, and it has MOSI connected to the "input" of the shift register, and MISO connected to the output of the shift register. The shift register is clocked by the SCK line.
SPI transfers bytes, so the SCK has to be 8 times faster than the loading of the shift register.