Sanity Check
Suppose you have a verfication enviroment for a design (either module or chip), if you have changed something in design then to see if there is no compilation/any other issue either in your design or verification enviroment, a very simple basic test is run to establish sanity of both verification enviroment and design.
Sanity test should be simple one not to check your DUT functionality but to establish sanity in verification enviroment.
Once sanity is done, then you can start verifying all the features of the design.
Hope this answers your query.
Regards,
pintuinvlsi