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Suppose you have a verfication enviroment for a design (either module or chip), if you have changed something in design then to see if there is no compilation/any other issue either in your design or verification enviroment, a very simple basic test is run to establish sanity of both verification enviroment and design.
Sanity test should be simple one not to check your DUT functionality but to establish sanity in verification enviroment.
Once sanity is done, then you can start verifying all the features of the design.
Sanity check is a literal term, its not a ASIC term. Ppl use the term 'sanity check' for almost anything they want to use it for. Usually these are kind of 'non urgent' checks.
For example : if I have a function which shifts an 'n' bit vector by an integer 'i1' you may want to put a 'santity check' in the function that will produce a warning or error, when 'i1' is greater than 'n'.
Another example of a 'sanity check' is already been given to you by pintuinvlsi
Hope this helps,
Kr,
Avi http://www.vlsiip.com
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