what is the problem with this signal assignment line?

[fahim1]

hi
in this code why the errors
"No feasible entries for infix operator "*""
"bad expression in left operand of infix expression "+""
"Bad right hand side (infix expression) in variable assignment." happened?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
entity serialm is
port(a,b : in std_logic_vector(3 downto 0);
  clk : in std_logic;
  out3 : out std_logic_vector(7 downto 0));
end serialm;
architecture serialm_arch of serialm is
  signal sum : std_logic_vector(2 downto 0) := "000";
  signal count :integer := 0;
  signal outtemp : std_logic_vector(7 downto 0) := "00000000";
  begin
    process(clk)
    variable sum0,sum1,sum2,sum3 : std_logic := '0';
    variable c0,c1,c2,c3 : std_logic := '0' ;
    variable temp0,temp1,temp2,temp3 : std_logic_vector(1 downto 0) :="00";
    variable inp :std_logic_vector(6 downto 0) := b(3 downto 0) & "000";
    
    begin
      if (clk='1' and clk'event) then 
        if (count <9) then
        temp0 := ( a(0) * inp(3) )+ c0 ;

this is also not the full code.
tnx

 

[fahim1]

hi
b is my input and this code have warning and i tthibk dont work properly tooo?
what is the solution?

 variable inp :std_logic_vector(6 downto 0) := b(3 downto 0) & "000";

 

[dpaul]

For both of your recent threads, please post the full-code along with the complete compiler generated error messages.

 

[fahim1]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
entity serialm is
port(a,b : in std_logic_vector(3 downto 0);
  clk : in std_logic;
  out3 : out std_logic_vector(7 downto 0));
end serialm;
architecture serialm_arch of serialm is
  signal sum : std_logic_vector(2 downto 0) := "000";
  signal count :integer := 0;
  signal outtemp : std_logic_vector(7 downto 0) := "00000000";
  begin
    process(clk)
    variable sum0,sum1,sum2,sum3 : std_logic := '0';
    variable c0,c1,c2,c3 : std_logic := '0' ;
    variable temp0,temp1,temp2,temp3 : std_logic_vector(1 downto 0) :="00";
    variable inp :std_logic_vector(6 downto 0) := b(3 downto 0) & "000";
    
    begin
      if (clk='1' and clk'event) then 
        if (count <9) then
        temp0 := ( a(0) * inp(3) )+ c0 ;
        sum0  := temp0(0);
        c0 := temp0(1);
        temp1 := (a(1) * inp(2))+c1 ;
        sum1  := temp1(0);
        c1 := temp1(1);
        temp2 := (a(2) * inp(1))+c2 ;
        sum2  := temp2(0);
        c2 := temp2(1);
        temp3 := (a(3) * inp(0))+c3 ;
        sum3  := temp3(0);
        c3 := temp3(1);
        sum <= (sum0 + sum1 +sum2 +sum3) ;
        outtemp(count ) <= sum(0);
        count <= count +1 ;
      elsif (count = 9 ) then 
        out3 <= outtemp(7 downto 0);
      end if;
      end if;
      --shift inp
    end process;
  end serialm_arch;

 

[FvM]

The assignment should be separated from the variable definition (after "begin").

 

[TrickyDicky]

a and inp are std_logic, not std_logic_vectors, so they cannot be multiplied
Thats like asking it to multiply a single bit by a single bit.

You also cannot add a std_logic to a std_logic. You can only add vectors (and you should not do arithmatic with std_logic_vectors, only unsigned/signed types)

 

[dpaul]

Your design may work, but it is better to following the "the golden rules of VHDL style coding".

Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements.

Better to keep the assignment of signals outside the process block.

Recommend this reading for you @ StackOverflow:
https://electronics.stackexchange.com/questions/115419/signal-assignment-in-out-process

 

[fahim1]

The assignment should be separated from the variable definition (after "begin").

its inp's first value and i shift it in each process and use the shifted value,i think if i defined it after begin in each process the initial value will be used,is it right?

 

[TrickyDicky]

Your design may work, but it is better to following the "the golden rules of VHDL style coding".

Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements.

Better to keep the assignment of signals outside the process block.

Recommend this reading for you @ StackOverflow:
https://electronics.stackexchange.com/questions/115419/signal-assignment-in-out-process

What? Signals should almost always be assigned inside a process. Only basic combinatorial signals should be outside a process.

 

[fahim1]

a and inp are std_logic, not std_logic_vectors, so they cannot be multiplied
Thats like asking it to multiply a single bit by a single bit.

You also cannot add a std_logic to a std_logic. You can only add vectors (and you should not do arithmatic with std_logic_vectors, only unsigned/signed types)

i thought if i add unsigned library i can do this,
it did this before and it worked properly in this code :

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;    --package needed for signed
--use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
-----------------------------------------
entity fir2 is
--generic  (n :integer :=4;   --number of coefficients 
          --m :integer :=4);   --number of bits represent coefficients
port( x : in std_logic_vector (3 downto 0);
      clk,rst : in std_logic;
      y : out std_logic_vector (7 downto 0));		
end fir2;
------------------------------------
architecture fir2_arch of fir2 is
type registers is array (2 downto 0) of std_logic_vector(3 downto 0);
type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0);
signal reg : registers := ("0000","0000","0000");
constant coef : coefficients := ("0001","0010","0011","0100");
-----------------------------------
begin
process(clk,rst)
variable acc,prod : std_logic_vector (7 downto 0) := (others => '0');
begin
-----------------reset--------------------
if rst='1' then 
   for i in 2 downto 0 loop
       for j in 3 downto 0 loop
		     reg(i)(j) <= '0';
		 end loop;
   end loop;
-------------register inference + MAC -----------
elsif (clk'event and clk='1')  then
acc :=  (others => '0');
acc := coef(0)*x ; 
prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0);
acc := acc + prod ;
reg <= x & reg(2 downto 1 );
end if;
y <= acc;
end process;
end fir2_arch;

 

[dpaul]

Oops...sorry! Careless Typo!
I meant assignment to o/p ports should be done outside the process block.
The thread starter was not doing it with the port 'out3'.

 

[FvM]

i thought if i add unsigned library i can do this,
it did this before and it worked properly in this code

Look sharp. Each factor in this code is a vector.

You can convert std_logic to single bit std_logic_vector

temp0 := ( a(0 downto 0) * inp(3 downto 3) )+ c0 ;

 

[fahim1]

Look sharp. Each factor in this code is a vector.

You can convert std_logic to single bit std_logic_vector

temp0 := ( a(0 downto 0) * inp(3 downto 3) )+ c0 ;

thanks but now i have warning Warning: [14] C:/altera/13.1/serialm.vhd(24): (vcom-1012) Slice range direction (to) does not match slice prefix direction (downto).

and i dont have enough time to change all my codes from std_loguc_vector to unsigned.

 

[TrickyDicky]

Oops...sorry! Careless Typo!
I meant assignment to o/p ports should be done outside the process block.
The thread starter was not doing it with the port 'out3'.

Again - why? an output is just like any other signal (except you cant read it) - so it can be assigned inside a process.

 

[fahim1]

a and inp are std_logic, not std_logic_vectors, so they cannot be multiplied
Thats like asking it to multiply a single bit by a single bit.

You also cannot add a std_logic to a std_logic. You can only add vectors (and you should not do arithmatic with std_logic_vectors, only unsigned/signed types)

there isnt any way to add std_logic to std_logic and myltiply std_logic to std_logic ???

 

[dpaul]

It would work. But is it best practice?

 

[TrickyDicky]

there isnt any way to add std_logic to std_logic and myltiply std_logic to std_logic ???

No. It wouldnt make any sense.
What is the answer for '1' * '1'? the answer would be '1'. WHy not just and them together?

- - - Updated - - -

It would work. But is it best practice?

Yes. Never seen seen anything wrong with it, or had it in coding guidlines
Ports on entities are just signals. Assigning an output inside a clocked process just infers a register - and that IS something that is often on coding guidelines - all outputs should be registered.

 

[fahim1]

No. It wouldnt make any sense.
What is the answer for '1' * '1'? the answer would be '1'. WHy not just and them together?

- - - Updated - - -



Yes. Never seen seen anything wrong with it, or had it in coding guidlines
Ports on entities are just signals. Assigning an output inside a clocked process just infers a register - and that IS something that is often on coding guidelines - all outputs should be registered.

if we have a signal assignment during the transient of another signal always will make extra registers??
why?
input and outputs always make registers???????

- - - Updated - - -

Look sharp. Each factor in this code is a vector.

You can convert std_logic to single bit std_logic_vector

temp0 := ( a(0 downto 0) * inp(3 downto 3) )+ c0 ;

i changed and i have warning does it work?

 

[FvM]

thanks but now i have warning Warning: [14] C:/altera/13.1/serialm.vhd(24): (vcom-1012) Slice range direction (to) does not match slice prefix direction (downto).

Apparently only Modelsim is complaining here, Quartus doesn't. Just check the results.

there isnt any way to add std_logic to std_logic and myltiply std_logic to std_logic ???

You can write equivalent logic expressions for the result bits. Presumed you know what the expected result is.

 

[fahim1]

if we have a signal assignment during the transient of another signal always will make extra registers??
why?
input and outputs always make registers???????

- - - Updated - - -



i changed and i have warning does it work?

will u please help me how to change it to unsigned?????/