Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
pipelining is efficient use of all resources at the same time. In 5 stage pipelining, all hardware resources will be processing data n saving in intermediate registers. hence speed of execution ie through put increases.
Google books has Computer Architecture: A Quantitative approach by Hennessey and Patterson. It has a chapter which tells you all about pipelining.
In digital circuit, its used to speed up the circuit. When you use pipelining the clock frequency is determined by the stage that has the maximum delay. Thats just the basic of pipelining and it has lot many more issues surrounding it.