Hi.
I am Verilog engineer.
I willing to learn SV and UVM, but they have amount of large pages.
So if you can advice me, could you please let me know where I have to start at SV and UVM?
Please let me know what should i know in order of important
if you have any knowledge about object oriented it will make it easy to learn system verilog, if not it will be helpful if you read more about Object oriented concept but not so deep only concept and then system verilog read "LRM 1800-2012" .
about UVM there is site called " Verification academy" for mentor graphics if you where able to join it you will find a lot about UVM for beginner and for intermediate videos(about 18 video each one around 20 min) and if you want more you can read uvm cookbooks from same site it was very helpful.