juansiahaan
Junior Member level 2
What is the meaning of a VHDL line like this :
and what is the difference when the values above are interchanged? (signal is 0 and signalx is 1)? I've seen some codes using that line but I haven't gotten the idea of that line...could someone explain me?
Thanks and regards,
Juan
Code VHDL - [expand] 1 if (signal = '1' and signalx = '0') then
and what is the difference when the values above are interchanged? (signal is 0 and signalx is 1)? I've seen some codes using that line but I haven't gotten the idea of that line...could someone explain me?
Thanks and regards,
Juan