What is the meaning of this VHDL statement?

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juansiahaan

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What is the meaning of a VHDL line like this :

Code VHDL - [expand]
1

if (signal = '1' and signalx = '0') then


and what is the difference when the values above are interchanged? (signal is 0 and signalx is 1)? I've seen some codes using that line but I haven't gotten the idea of that line...could someone explain me?

Thanks and regards,

Juan
 

Strange question. That line means that if signal=1 and signalx=0 then the following lines will be executed.
 

Maybe it is a part of edge detection. with the code below you can detect edges on 'signal'.

if (rising_edge(clock)) then
signalx <= signal; -- signalx is delayed (1clock period)
if (signal='1' and signalx='0') then -- rising_edge
--...
elsif (signal='0' and signalx='1') then -- falling_edge
--...
end if;
end if;
 


Yes that's what I mean...but is it the same when I use rising_edge (signal) or falling_edge (signal)?

I guess there can only be one rising_edge or falling_edge in a process...isn't it? Does that imply that if I want to detect a rising or a falling edge of another signal I can use that syntax if a rising_edge syntax has been previously used (such as rising_edge (CLK))?
 
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This only works if the signal you're sampling is at no more than half the frequency of your clock. Look at it this way: whether you are using rising_edge or falling_edge, you are taking a sample of the state of your input signal and comparing it to the state of the signal on the previous clock.
 

The rising/falling edge function is for detecting falling edges on signals in VHDL - eg. detecting clock edges. They are NOT synthesisable other than for clocks.
To detect rising and falling edges of a signal in a synchronous environment, you need to register the source signal (like with signalx) and check the delayed and non-delayed version on a clock edge. You cannot use the rising edge function for this, because these functions can only check 1 signal, not two.
 

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