hi,
i am trying to do the a frequency divider by 2 by using the DflipFlop
The design just simple where the output of the DflipFlop is feedback to input of the DFF... While i run the compilation the ALTERA QuartusII not allow the input to be feed directly from the output. Anyway to solve this kinda problem? Thanks
Oh... by VHDL ... [/img]
ops...sorry, the feedback loop going to hv a inverter...
Nandy, just to clarify, do u mean, we first reset the flipflop first then the output will be LOW (0) can cause the input to be '1' ?