Re: what is gate level??
RTL: the description is divided into combinational logic and storage elements.The
storage elements (flip flops, latches) are controlled by a system clock. The
description is synthesizable.
GATE: the design is represented as a netlist with gates (AND, OR, NOT, ...) and
storage elements, all with cell delays. The description has been synthesized.
An RTL description is usually converted to a gate-level description of the circuit by a logic synthesis tool.