If you look at the basic component both SRAM (compilers) and Registerfile involve SRAM (memory cell) and logic.
But Registerfile is designed high speed where as in SRAM (compilers) are designed for better area and power also.
Also the range (memory capacity) supported registerfile is much lesser than the range supported by the SRAM.
Is this question arise from the choice of SRAM memory compiler and registerFile memory compiler?
I did some study sometime back on the different but cannot remember the exact different now. Anyone know the basic different in functionality (not just how it is implementated). One of the different I can remember is related to a register file can have a separate read and write clock, but only one output, but memory will be a full dual-port type... not sure at all now.
how can 1 T implemwnt a SRAM. SRAM should have a loop to maintain the value while DRAM use cap. as i know register array using DFF just for low volume to avoid the area for the RAM decode circuit and some other overhead.