what is the difference of Registerfile and SRAM?

[godsun]

registerfile is faster than SRAM and more power consuption, i don't know why
it is seem that they are same timing...

Registerfile = control logic + SRAM ???

 

[nitu]

If you look at the basic component both SRAM (compilers) and Registerfile involve SRAM (memory cell) and logic.
But Registerfile is designed high speed where as in SRAM (compilers) are designed for better area and power also.
Also the range (memory capacity) supported registerfile is much lesser than the range supported by the SRAM.

 

[incisive]

Sram uses 1-6T cells, gates, according to the technology.

 

[mopengfei]

Registerfile
comprise of resgister --such as DFF, flip-flop

but the SRAM

Sram uses 1-6T cells, gates, according to the technology.

the teches is different--

 

[leeenghan]

Hi,

Is this question arise from the choice of SRAM memory compiler and registerFile memory compiler?

I did some study sometime back on the different but cannot remember the exact different now. Anyone know the basic different in functionality (not just how it is implementated). One of the different I can remember is related to a register file can have a separate read and write clock, but only one output, but memory will be a full dual-port type... not sure at all now.


Regards,
Eng Han
www.eda-utilities.com

 

[stevepre]

RF is asynchrounous read
SRAM is synchronous read

for small stuff, use RF. For larger one, use SRAM.

 

[AlexWan]

This topic had been discussed.

Some guys maybe refer the following link:

 

[JesseKing]

Sram uses 1-6T cells, gates, according to the technology.

I don't think the sram cell can be implemented with 1T, it's a DRAM cell.

 

[eexuke]

Sram uses 1-6T cells, gates, according to the technology.

I don't think the sram cell can be implemented with 1T, it's a DRAM cell.

I do see 1T-SRAM cells in sony's chip. But at that time 1T-SRAM has some stability problems.I don't know whether it has been improved now.

 

[woodyplum]

Sram uses 1-6T cells, gates, according to the technology.

I don't think the sram cell can be implemented with 1T, it's a DRAM cell.

I do see 1T-SRAM cells in sony's chip. But at that time 1T-SRAM has some stability problems.I don't know whether it has been improved now.

how can 1 T implemwnt a SRAM. SRAM should have a loop to maintain the value while DRAM use cap. as i know register array using DFF just for low volume to avoid the area for the RAM decode circuit and some other overhead.

 

[clj023]

I agree with the second reply.

To same capacity ram:
REG---high speed more area consume
SRAM--- low speed less area consuem

Added after 6 seconds:

I agree with the second reply.

To same capacity ram:
REG---high speed more area consume
SRAM--- low speed less area consume