What is the DIfference between these synchronous codes... Are the similar

[syedshan]

Dear all,

I have a synchronous system I am just placing the sample of my code, it is not the actual code since actual code includes
many complex naming signals. But please look into it.

What is the difference between following two codes for a synchronous signal in terms of function

I think both the system are functionality wise same. Can any one comment.

Code 1

always@(posedge clk)
begin
if(rst) a=0; b<=0; cnt<=0;

else 
      if(cnt==0) begin a<=10; cnt<=cnt+1; end
      else if(cnt==1) begin a<=20; cnt<=cnt+1; end
      else begin cnt<=0; a<=30; end
end


always@(posedge clk) 
begin
if(rst) sum<=0;
else 
case(cnt)
1: sum <= a;
2: sum <= sum+a;
3: sum <= sum +a;
default: 
endcase
end

Code 2:

always@(posedge clk)
begin
if(rst) begin a=0; b<=0; cnt<=0; sum<=0; end

else 
begin
      if(cnt==0) begin a<=10; cnt<=cnt+1; end
      else if(cnt==1) begin a<=20; cnt<=cnt+1; end
      else begin cnt<=0; a<=30; end


case(cnt)
1: sum <= a;
2: sum <= sum+a;
3: sum <= sum +a;
default: 
endcase

end

PS: Ignore the Syntax error since I dont mean to check syntax

 

[gongdori]

I'm not verilog person, but doesn't the code at the top generate registers for "sum" signal, but not for the bottom code?

 

[syedshan]

Well both the cases will of course generate the register for sum

What I meant is related to timing functionality, in the earilier, will the two blocks will run one after other (w.r.t clk cycles) or what..?

---------- Post added at 11:14 ---------- Previous post was at 11:14 ----------

Well both the cases will of course generate the register for sum

What I meant is related to timing functionality, in the earilier, will the two blocks will run one after other (w.r.t clk cycles) or what..?

 

[gongdori]

Oh, my bad. I thought the sum signal was not the part of the always statement.
Since both codes are synchronous and are only activated at the rising edge of clk signal, I would say they are identical.
Again, I am beginner in Verilog.... :razz:

 

[FvM]

Yes, both are identical. The LHS of non blocking assignments is set after a clock cycle. No matter, if they are placed in one or two always blocks.