What is the difference between test vectors ,cases & ben

[mallikmarasu]

regarding testbenches

hi ,
what is the difference between test vectors ,test cases and test benches.
how to write test cases to a design?
in industry what sequence of steps follows to write a test bench?

plz give valid points and good materials

regards
mallik

 

[dtn_me]

Re: regarding testbenches

From rtl simulations point of view, test vectors & testcases hold same meaning. Testbench provides inputs to the design(RTL) and expects an output. For this operation( Testbench provide proper inputs to rtl and rtl responds in proper way), to happen, we need to configure bothe rtl & TB registers. This configuring part is taken over by testcase(or testvector). Testcase, programs testbench & DUT registers and initiates the operation mode. Once TB gets expected response from design, testcase will inform the result to us.

From DFT view, testvector is different and no testcase here. In DFT, testvector is a sequence of binary numbers(1's & 0's) which will go into flops as a chain and come out from scan_out pin of the design. The input test vector is compared with output test vector to find if there are any faults in the design.

Regards
DTN

 

[mssajwan]

regarding testbenches

Hi,
Test vector & test cases hold the same meaning as far as verification is concerned.
Testbench is an environment where you have testbench component like protocols,checkers,monitors etc & RTL instance.

you apply test inputs through Testcases.
Now testcase can be in any form, static or dynamic.
dynamic ones are asm cases.

-regards
-Manmohan