Re: synthesis
I am sorry - I have to disagree with a couple of the answers above.
Physical Synthesis, in the context of ASIC design is the process in which physical layout of gates is considered while performing synthesis. This means that the effect of the location of placement of the gates is considered in making synthesis choices. In normal synthesis, the physical aspect of the layout is not accurately considered, instead an approximation based on wireload models is used.
In FPGAs, physical synthesis is an iterative process which considers placement while making packing & re-synthesis optimizations.
Please see
**broken link removed**