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synthesis is conversion of rtl to high level gates .this is doing in front end designer
physical synthesis is conversion of (netlists)high level gates to transistor level logic.this is doing in backend designer
I am sorry - I have to disagree with a couple of the answers above.
Physical Synthesis, in the context of ASIC design is the process in which physical layout of gates is considered while performing synthesis. This means that the effect of the location of placement of the gates is considered in making synthesis choices. In normal synthesis, the physical aspect of the layout is not accurately considered, instead an approximation based on wireload models is used.
In FPGAs, physical synthesis is an iterative process which considers placement while making packing & re-synthesis optimizations.
synthesis is a front end job
and physical synthesis is a backend job
Synthesis is a simple terms conversion of ur RTL code to Gate level netlist
I hope u know netlist has only the interconnect information
and Physical Synthesis is working from Netlist to Tapeout or Masking information that is given to foundry for manufacturing ur chip
what some ppl are saying about wireload models are absolutely having half knowledge and based on PDFs not actual work
wireload models are based on area and fanout or can say input transition and output load on a Cell which are used to ESTIMATE the delay in pre layout STA as actual placement of cell is not known hence the routing delay is not known which is established in the Physical Synthesis flow
after placement we have actual location of that cell thus we know the actual distance and hence the exact delay is known
now this info is used in Post Layout STA