[SOLVED] What is the difference between HV SOI and HV CMOS process?

[rissenaj]

Hi all,

I am doing a high voltage driver design and I have come across several designs some of which are implemented in HV-SOI and some in HV-CMOS. Could someone please tell me what is the difference between both and when each is used. Thanks in advance.

Regards
rissenaj

 

[erikl]

HV-CMOS usually needs larger-sized transistors than HV-SOI, and - depending on the HV value - sometimes additional guard rings, which need a lot of area.

So HV-SOI designs need less area, produce smaller parasitic capacitances, hence can be used up to higher frequencies.

SOI is more expensive than bulk CMOS.

 

[rissenaj]

HV-CMOS usually needs larger-sized transistors than HV-SOI, and - depending on the HV value - sometimes additional guard rings, which need a lot of area.

So HV-SOI designs need less area, produce smaller parasitic capacitances, hence can be used up to higher frequencies.

SOI is more expensive than bulk CMOS.

Thanks for the response. Is the IBM 7HV process [ftp://public.dhe.ibm.com/common/ssi/ecm/en/tgd03019usen/TGD03019USEN.PDF] a HV-CMOS process? Could you please give an example of an HV-SOI fabrication process.

Thanks
rissenaj

 

[erikl]

Is the IBM 7HV process [ftp://public.dhe.ibm.com/common/ssi/ecm/en/tgd03019usen/TGD03019USEN.PDF] a HV-CMOS process?

See here ...

Could you please give an example of an HV-SOI fabrication process.

... and here!