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I believe clock jitter is the delay from the output of the clock generated circuit to the port of the clock pad.
So this mean clock jitter is a internal delay within the clock pad which need to be consider by the digital enginner.
To make this statement clearer, clock uncertainty is the different between 2 clock path from the port of the clock pad. Clock uncertainty is external delay from the clock pad and clock jitter is the internal delay within the clock pad.
Clock Jitter is the variation in clock period, ac123 is right.
But the reason must be discussed. It may come from the circuit that is not well designed or assembled, or cannot be avoided and must be accepted, then the designer must know it and take it into accounts when designing.
It also may come intentionally. Say, you need to design a alarm digital clock with a very small tolerance in time. So the time must be accurate within a minute, or an hour, a day, a week, a month, etc., but your clock source cannot provide the precise second clock pulse of 1000ms, for example, this pulse is 1010ms. So you have to use this pulse, and then shorten the other pulse so that, for one minute you will get totally 60 second pulse of precise 60s. The sympton of clock period, while must be constant over time, varies within a very short time duration called clock jitter.
Clock Jitter may come due to some noise in the clock generating circuit, like PLL.
This is more predominant at high frequencies, it even effects setup and hold time violations in some designs which are having critical paths. If we use DLL instead of PLL then we can reduce jitter in clock.