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what is test case,test vector,test bench?

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omkar

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Hi all,
I am very new to verification.I know these are very basic terms. can anyone tell the difference between these terms with some simple verilog programs if possible.
Thanks
 

darylz

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according to the "test case", "test bench" generate "test vector" and output to DUT, the result is also checked by "test bench".
"test case" is defined manully according to the design spec.
 

    omkar

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avimit

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Agreed with darylz.
To elaborate further:
let us take a design, say an ALU which can do some artithmatic and logic operations.
A typical 'test case' would be to say test 'ADD' function of alu, another 'test case' would be to say test 'MULTIPLY' function of the Alu and so on and so forth.
The inputs you would apply to the design to test a particullar 'test case' would be a set of 0s and 1s which is called a 'test vector'.
All these things you are going to do using a language may be vhdl verilog or 'e'. The model you will write to do all this will be called 'test bench'
hope it helps
kr,
Avi
https://www.vlsiip.com
 
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    omkar

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omkar

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Hi Darylz and Avimit,
Thanks for the reply.

Hi Iouri,
The link has been removed.Can anyone provide any other links regarding testbenches.
 

Iouri

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Link works fine, try to copy and paste link in to your browser window
 

ameed

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hi all,

to see some vhdl and verilog tutorials.

and also refer some text books e.g. vhdl primer by bhashakar.

thanx.......
 

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