Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is switching frequency limitation when BJT used for slope compensation?

Status
Not open for further replies.
T

treez

Guest
hello,

I am doing a flyback SMPS, and using the clock ramp of the pwm controller to derive the ramp for slope compensation.

I am using a BJT to buffer the clock signal, as i dont want to load the clock down and mess up the performance of the controller.

...here is the BJT shown buffering the clock ramp....



BJT to buffer the clock ramp for slope compensation
https://i45.tinypic.com/r8v8ck.jpg



....obviously , BJTs such as 2N3904 have a certain switching time, and i wondered how high in clock frequency this BJT circuit can be effective for?
.....eg suppose that the clock was ramping at 500KHz.......would the 2N3904 be able to "keep up" with this?

2N3904 DATASHEET:
https://www.fairchildsemi.com/ds/2N/2N3904.pdf
 

G'day,

The particular BJT (from datasheet) has an Ft of 300Mhz meaning at unity gain it will work at 300MHz... However, you have a fair resistance in the emitter which means your fall time could be a little slow... but so long as you're not saturating the BJT I would think you should be OK... the fact that LT don't shed much light on the component values surrounding slope compensation in their datasheets makes me think there might be a bit of trial and error involved - minimized of course with the best educated guess'!

That said... there are quite a few current mode controllers around that take care of slope compensation internally (more so than not i would think).

Good luck!
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Thanks ThunderDanTheMan

The BJT is thankfully not saturated........due to the collector is clamped to VREF=5V, and the emitter is 0.7V below the base, and the base is connected to the oscillator clock pin....................so it cannot saturate.......and i take saturation as meaning any event which makes the BC voltage go positive........ie, the BC diode forward bias's.
 

As long as it's not saturating or cutting out, it's not really switching, and you can treat it as a linear amplifier. In that case its bandwidth should be plenty high. So you just need to make sure the ramp doesn't go low or high enough to bring it out of its linear region.
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Can you show the Rt/Ct waveform, particularly minimum voltage? It's not in the datasheet. Preferably a real measurement.

If the voltage is swinging too low, a JFET could be used as buffer.

P.S.: In standard current mode controller, e.g. 3842, the ramp voltage is about 1.2 V min, 2.8 V max. A similar range should be O.K.
 
  • Like
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
sorry FvM i havent done the PCB yet....the range you give is right though.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top