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What is Pseudo-E and Pseudo-D logic design ?

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Dnyanesh993

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In the field of organic/inorganic semiconductor devices implementing the digital logic with the help of CMOS logic is somewhat difficult due to the unipolar nature of the devices. So to implement a digital logic some research papers have provided the method of Pseudo-CMOS. In which they implemented the logic by using some terms like Pseudo-E and Pseudo-D logic. So, can tell me what these terms signify.
 

dick_freebird

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Enhancement and Depletion perhaps? Which pertain to
MOSFETs and maybe not organic devices, hence the
"pseudo"?

Earliest MOS logic were depletion-load PMOS (NMOS
being unreliable until mobile ion contamination and
gross oxide charge trapping got controlled). The MOS
devices would be fabricated with two different VT
implants (or natural bulk doping, and one adjust
implant where needed).
 

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