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IO cells - provide interface to the external world (i.e. to other chip).
The have I/O driver circuits, level shifters, ESD protection circuits, etc.
And Pull up/down circuits, three-state buffers in some cases
The input and output signals may be at some voltage level (say 3.3V). But the core may be working at some other voltage level (say 1.2V). The IO cells have in-built level shifters to shift the voltage to desired level.
The output drivers strengthen the signal so that the output pin can feed the signal to other chip(s).
Spare cells contain few gates like DFF, NAND, buffers, inverters etc. These cells are spread over the die. If there is a change in the netlist (ex: some extra logics are added), instead of doing the entire design from scratch, we can do ECO.
The spare cells are used to implement the necessary logic thereby keeping the placement intact. Only few changes have to be made in the routing.
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