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most EDA support tcl. it's very easy to learn and good enough for EAD scripts. Perl is a powerful (maybe the most powerful) script language and can do many things. But you should not spend time on Perl if you only focus on FPGA design.
PERL is a scripting tool, and faciliates text processing jobs. It is not directly applicable to FPGA design, but it can spped up your design process by reuseing, also it's capability on text proccesing can ease your design entry step. Another application is large log file processing.
Perl only helps in maintaining the EDA tool during design, it won't help in actually designing the FPGA per se. Many tools might support tcl instead such as Synplify and ModelSim. Learning Perl could prove to be harder than the HDL itself.