What is Pausable clocking?

[vibhute_r_p]

HAs any one done any experimentation with pausable clocking? What does it mean? CAn you provide some VHDL or verilog code?

 

[nand_gates]

Hi,
Using google search I got this!!
www.ece.rochester.edu/~yozhu/ comparch-seminar/Clock_Synchronization.pdf

Hope this helps

 

[yeewang]

pausable clocking?

simply that the clock can be paused and resumed without interfering logic operations, I think.

 

[floatgrass]

always @ (posedge clk or negedge clear)

if(!clear)

clk_2 <= 0 ;

else

if(!en_n)

clk_2 <= ~clk_2 ;

else

clk_2 <= clk_2 ;