What is Pausable clocking?

vibhute_r_p · Jan 6, 2005

HAs any one done any experimentation with pausable clocking? What does it mean? CAn you provide some VHDL or verilog code?

nand_gates · Jan 6, 2005

yeewang · Jan 7, 2005

pausable clocking?

simply that the clock can be paused and resumed without interfering logic operations, I think.

floatgrass · Jan 8, 2005

always @ (posedge clk or negedge clear)

if(!clear)

clk_2 <= 0 ;

else

if(!en_n)

clk_2 <= ~clk_2 ;

else

clk_2 <= clk_2 ;

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