What is Negative limit replaced by 0 ?

[wls]

+neg_tchk

Hello . I use vcs to run gate simulation with backannotate sdf , and got message required + neg_tchk . I then add +neg_tchk to my testbench script , but got "SDF Warning: Negative limit replaced by 0 ".
I check verilog module YCDF5 , and it have the $setuphold construct in it .

Shouldnt , it able to handle negative setup ?


********
SDF Error in instance tb_top.dut.y_reg_0_ of module YCDF5:
./alumimos_se.sdf:453, SDF Error: Negative SETUP needs +neg_tchk, replaced by 0
********

SDF Warning in instance tb_top.dut.y_reg_0_ of module YCDF5:
./alu_se.sdf:453, SDF Warning: Negative limit replaced by 0, use $setuphold in the Verilog source.
SDF Warning in instance tb_top.dut.y_reg_0_ of module YCDF5:
./alu_se.sdf:456, SDF Warning: Negative limit replaced by 0, use $setuphold in the Verilog source.
SDF Warning in instance tb_top.dut.y_reg_1_ of module YCDF5:

 

[woodyplum]

negative limit

Negative limit replaced by 0 should be safe in the circuit design, while it will cause the mismatch between the STA and the VCS, if you use the setupholod timing check in your model and turn on the negchek(or some like this in vcs manuan) switch, it should be back annanotated.

 

[wls]

neg_tchk

Hello woodyplum . How do we be sure that negative limit or negative setup/hold is safe in signing off a design simulation .

That is some thing taht I been trying to find answer ? Are there any code sample that have these test case and helps to verify that it is safe ?

What could cause negative limit ?

Regards.