What is "kick back noise"?

[whaler]

kickback noise

I encountered a guideline called "kick back noise" in the design of a dynamic comparator. But I am not quite sure what it means and how to calculate or simulate the noise. Please help me. Thanks a lot!

 

[okguy]

kick back noise

It is basically the noise from the switching first stage on the input of your comparator.
If the output of the first stage swing quickly in large range, it will make a glitch at your comparator inputs. The effects is worst if they are driven by high impedance (in switched cap circuit for instance). Then, you get an offset.

 

[crazyamd]

kickback voltage

the so called kick-back noise comes from the high swing stage such as the latch to the comparator input.

 

[alchen77]

what is kickback noise

It is basically the noise from the switching first stage on the input of your comparator.
If the output of the first stage swing quickly in large range, it will make a glitch at your comparator inputs. The effects is worst if they are driven by high impedance (in switched cap circuit for instance). Then, you get an offset.

I understand your explaination but can you give me a detail explain for the offset.
If in switched cap circuit why not open the high impedence path??
Is the offset created by the different impedence??

thanks very much.

 

[field_catcher]

comparator kickback noise

I am really interested in knowing how the "kick back noise" is generated. I designed a comparator with this problem, I have been trying to elminate the kickback noise, but I found it is difficult to just modify the comparator without changing the driving condition.

Anyone has any good example to explain the scheme?



P.S: I don't think it should be called "noise" as it really is deterministic. Do you agree? Maybe it is used the same way as we call quantization error "quantization noise".

 

[rockycheng]

comparator kickback

If timed appropriately, a multi-stage comparator with capacitors between each stage could be used to eliminate the kick back (or clock feedthrough) error.

 

[maxwellequ]

kickback comparator

I'm also interested in this subject. Some time ago I was making a search and I found:

**broken link removed**

The description is suggestive. Can anyone upload this ?

Thanks

 

[krashkealoha]

kickback noise

Here's the paper:

Low kickback noise techniques for CMOS latched comparators
Figueiredo, P.M. Vital, J.C.
Chipidea Microelectron.,, Porto Salvo, Portugal
This paper appears in: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Publication Date: 23-26 May 2004
On page(s): I - 537-40 Vol.1

Abstract:
The latched comparator is utilized in virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. Such high voltage variations in the regeneration nodes are coupled to the input voltage - kickback noise. This paper reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations verify the effectiveness of our techniques.

 

[chody]

calculate kickback voltage

The kickback noise is concerned by input driving ability at comparator.

If input driving ability is stronger than comparator latch, the kickback noise is not concern about comparator function any more.

regards,

eyes146@hotmail.com

 

[chenjia]

kickback in latches

Then can this noise do something bad to bias circuits?

 

[Alan_Nesta]

kick back noise basics

it will make your input common voltage tremble,
so maybe large offset will generate

 

[layes2]

noise kick back

due to cgd maybe

 

[man_5684]

kick back noise wiki

can any one tell me how to measure it in comparator circuit(in my case it consist of a diode connected load preamplifier and a regenerative latch). how to analyse the result?????????

 

[kranthi_m]

Assume a NMOS whose gate is driven with a constant voltage by a voltage source with finite series resistance. Any MOS will have finite paracitic capacitance between its gate-drain and gate-source junctions. Reactance of this Capacitor is 1/ωc.
Now assume there is a voltage switching from 0-VDD at the drain with sharp rise time. The sharper the rise time the higher the frequency components present in the signal. The higher the frequency the lower is the reactance of the paracitic capacitor between Drain and Gate. This means there is a small impedance between drain and gate which can be approximated as a short between drain and gate. So, the voltage on drain during the rise time adds to the gate voltage and the net gate voltage rises.
This unwanted rise in the gate voltage is called kick-back noise.

 

[bappada_dgp]

Re: kickback noise

Thanks for the paper

 

[start-compar]

Assume a NMOS whose gate is driven with a constant voltage by a voltage source with finite series resistance. Any MOS will have finite paracitic capacitance between its gate-drain and gate-source junctions. Reactance of this Capacitor is 1/ωc.
Now assume there is a voltage switching from 0-VDD at the drain with sharp rise time. The sharper the rise time the higher the frequency components present in the signal. The higher the frequency the lower is the reactance of the paracitic capacitor between Drain and Gate. This means there is a small impedance between drain and gate which can be approximated as a short between drain and gate. So, the voltage on drain during the rise time adds to the gate voltage and the net gate voltage rises.
This unwanted rise in the gate voltage is called kick-back noise.

Your explanation is really clear and helpful !!

 

[april1975]

The explaination by Kranthi was very good.
What's about simulation? Does anyone simulate a comparator with kickback noise? Can we see it in plots as a simulation result?