if you are looking for set_input_delay & set_output_delay, then here is the answer:
set_input_delay is sets input path delays
Added after 8 minutes:
if you are looking for set_input_delay & set_output_delay, then here is the answer:
set_input_delay is sets input path delays on input ports relative to a clock edge.
meaning, if you have
clock period = 10
input delay = 3
Thus, your data will be arrived after 3.
Same thing happen when you set "set_output_delay"
#You can check this in Design Compiler user guide or you can read any synthesis books.
Hope it helps