irun2
Member level 2
This question seems to be stupid but I really need clarification. My understanding is that we can use EDA tool such as Verilog-XL to do gate-level simulation with the post-layout, or the netlist that after DC synthesis.
But my colleague told me that's not gate-level simulation, I have to do the simulation using AMS, (use the netlist to generate a symbol then setup a circuit schematic for simulation) like the Transient analysis.
But my colleague told me that's not gate-level simulation, I have to do the simulation using AMS, (use the netlist to generate a symbol then setup a circuit schematic for simulation) like the Transient analysis.