Snapback is in fact desirable and key to good NMOS-as-clamp
(or self-protection) ESD performance. You -want- a low holding
voltage (but greater than any spec load condition).
The other key is, the snapback current needs to be spread as
uniformly as possible ofer the device area. This wants drain
"ballasting" (distributed resistance, which the drain extension
may provide adequately or not; in my experience a silicide-block
(drain doped) resistive region, its length arrived at empirically
and width left to "be what it must, for threat level" is how the
device design unrolls.