what is "delay_mode_unit" for ncverilog?

[quan228228]

+delay_mode_unit

what is "delay_mode_unit" for ncverilog tool?

Could you give me an example?


thanks!

David

 

[avimit]

nc verilog timescale

When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity. It is used while running nelist sims, to just make them faster.
Kr,
Avi
http://www.vlsiip.com

 

[quan228228]

delay_mode_unit

When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity.
Avi
http://www.vlsiip.com

Where, what does "unity" mean?

David

 

[avimit]

delay_mode_unit ncverilog

unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is

 

[quan228228]

ncverilog no delay

unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is

for example;

timescale 1ns/1ps

assign #3 a = b&c;

after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right?

David

 

[beta0]

ncsim assign # delay mode

unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is

for example;

timescale 1ns/1ps

assign #3 a = b&c;

after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right?

David

no, delay mode is used for cell delay