Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In a nutshell , the placement will try to place in such a way as to minimize the wirelength of the design. In this type of placement, the first cost function is congestion and rest like timing/area/power etc are secondary cost functions. So,its a trade off the tool makes.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
