What is "Boundary scan"?

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Hi,

I'm a novice to VHDL & CPLD. I keep reading this exprission.
Can anybody tell me where to find technical infos about "Boundary Scan" ?

Thanks in advance.
 

All specification has been defined in IEEE 1149.1 which defined the Boundary Scan and its provision on chip. The boundary scan is a on-board testing provision, refer to the specification for more details.

Copy of specification can be found in MCU fileman under specifications.

Rgs
Rayengine
 

Good introduction to Boundary scan
 

Other document about Boundary scan:
h**p://hem.hj.se/~mabe/Master_2002/SysVerif_Test/Bound_Scan.pdf
 

For people that are too lazy to RTFM.

Boundary scan was conceived to allow for testing the interconnect between components on a board. An ASIC with boundary scan has an addtional register in each of the IO pads and all of the IO pads are connected to their neighbors to form a ring. This way a bit pattern can be shifted in to drive an output to a desired state and an input can be latched. The latched input values are then shifted out to be read by the board tester.

Radix
 

By referring to Synopsys's documents (SOLD) you can find very good information on this.
 

This is the boundary scan user guide!

Added after 5 minutes:

This is the boundary scan user guide and may help you!
 

Thomson said:
This is the boundary scan user guide!

Added after 5 minutes:

This is the boundary scan user guide and may help you!
Click to expand...

**broken link removed**
 

Take a look at this.. This is boundary scan for XILINX FPGAs

h**p://www.xilinx.com/xlnx/xil_tt_gettingstarted.jsp?sProduct=JTAG&iLanguageID=1

with regards,
 

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