Mar 23, 2015 #1 R ruwan2 Member level 5 Joined Nov 29, 2011 Messages 90 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 2,141 Hi, I see the following on the language reference document. After I look around for some time, I still do not understand what "A a1()" means. Could you help me on this question? Thanks, module top; A a1(); B b1(); endmodule module A; electrical n,p; branch (n,p) b; analog V(b) <+ 1.34; endmodule module B; analog $strobe("voltage == %g", V(top.a1.b)); endmodule Click to expand...
Hi, I see the following on the language reference document. After I look around for some time, I still do not understand what "A a1()" means. Could you help me on this question? Thanks, module top; A a1(); B b1(); endmodule module A; electrical n,p; branch (n,p) b; analog V(b) <+ 1.34; endmodule module B; analog $strobe("voltage == %g", V(top.a1.b)); endmodule Click to expand...
Mar 23, 2015 #2 mrflibble Advanced Member level 5 Joined Apr 19, 2010 Messages 2,720 Helped 679 Reputation 1,360 Reaction score 652 Trophy points 1,393 Activity points 19,551 Look under "Instantiating a module" here: https://www.asic-world.com/verilog/syntax2.html