What is a1() in this verilog-AMS code?

[ruwan2]

Hi,

I see the following on the language reference document. After I look around for some time, I still do not understand what "A a1()" means.

Could you help me on this question?


Thanks,

module top;
A a1();
B b1();
endmodule
module A;
electrical n,p;
branch (n,p) b;
analog V(b) <+ 1.34;
endmodule
module B;
analog $strobe("voltage == %g", V(top.a1.b));
endmodule

 

[mrflibble]

Look under "Instantiating a module" here: https://www.asic-world.com/verilog/syntax2.html