# What is a Frequency Doubler?

Status
Not open for further replies.

#### kumar_eee

What is freq.doublr?.. How to implement it using gates?...

##### Full Member level 4
clock frequency doubler

Hi kumar_eee,

Normally that is means a PLL, it's analog domain. You can find basic theory of PLL in many analog design book!

#### hr_rezaee

Frequency Doubler

freq.doublr is a device that output freq is double of input freq.
use PLL and a freq devider to have a freq.doublr

#### Davood Amerion

Frequency Doubler

use INVerter gates to delay clock and connect original clock and delayed clock to inputs of XOR.
at XOR output you have frequency which is twice of input frequency.

#### electronics_kumar

Re: Frequency Doubler

Davood Amerion said:
use INVerter gates to delay clock and connect original clock and delayed clock to inputs of XOR.
at XOR output you have frequency which is twice of input frequency.

WE WILL GET ONLY A SINGLE dc SIGNAL..I'M RIGHT

#### kumar_eee

Re: Frequency Doubler

Hi Davood Amerion,
U r correct.... Just now I got it...

Thanks,

K.Kumar

#### Matrix_YL

Frequency Doubler

hi all

Code:
module double ( clk, clkout);
input       clk;
output     clkout;
wire        inv_clk;

assign    inv_clk=~clk;
assign    clkout =inv_clk ^clk;

endmodule

why I get a low level (0) signal? XST synthesised it as a ground .
Or maybe I misunderstood your method ?

#### Davood Amerion

Frequency Doubler

in your code ~CLK not delayed.
it must delayed and xored with clk.

#### echo47

Frequency Doubler

Matrix_YL, your code logically simplifies to just a zero. You can apply the KEEP constraint to inv_clk to prevent it from being optimized away. See this similar example:

However, I don't recommend relying on gate delays in FPGAs. Shortcuts like that may come back to haunt you someday. In this case, it is much better to use a frequency multiplier provided by the FPGA, such as the Xilinx DCM block.

Status
Not open for further replies.