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Why we are not connectng VDD directly to a gate of a MOS?Usually through a tie high or tie low cell only we will connect.
Why its flagging as ERC error?
This can be an oxide integrity threat. Tying through
a "tie_" cell ensures that any gate current will be
limited should there be an overvoltage event (like
a supply spike) and the gate will have some
chance to survive even if broken down momentarily.
Attached to the rails and their on and off chip
decoupling, any "slightly weaker" gate oxide areas
in the design can receive "unlimited" current and
hammer the ones that break down earlier than
the rest. There's always that "tail" in the population.
But I also think this has taken on a "religious" aspect
and is laid down as a rule without any real science
being done "per process".
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