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what happens when fpgs is overloaded???

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Full Member level 4
Jul 23, 2006
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Hi friends,
I have a question.Can anyone tell me what happens when fpga is overloaded??I am writing an application for which my fpga crossed 100%.I am curious to know what happens to the fpga??

Are you serious?

I cant believe you dont understand what your implementation tools just indicated.

Basically what you are being told is that the device you have chosen is not large enough to implement the hardware your code is going to generate. You will need to either try to optimize your code, your layout, or move to a larger device.

As to what happens to the FPGA....nothing because it wont be loaded with bit stream.


nothing, you will not be able to generate *.rbf or *.bit file

You can never overload the FPGA. you can't burn it at all. You need to target another FPGA or try to optimise the design.

sorry for my late reply,
actually what happened was,when i synthesized my program it was showing as 110%.
so i had this doubt,
my question is will my tool XILINX optimise my design more in order to fit into fpga or should i optimise my design my reconsidering my code??

Please let me know...

The ISE will do some optimisation and possiblely reduce you design to < 100%.
If it can't, the tool will tell.
Anyway, you won't get your timing closure for that kind of resource utilization.

ISE will do some optimiztion, but you max design should be around 85% from targeted FPGA

In the case of Xilinx: don't forget that the router is inclined to "expand" the logic into all available resources. So even if the occupancy of available slices has reached 100% it does not mean you are nearing a full FPGA. There are switches "pack unrelated logic" that can further force the router to put things closer together and use more of the logic within each slice.

Of course, this might come at the expense of some more difficult routing, i.e. either more compilation time or slower logic speed.

So check the number of flipflops and LUTs, not the overall slice usage percentage it reports after routing. And of course the % of scarce resources like block rams and other special components.

In this case , when FPGA is overloaded....means your code design will not fit into the device which u have selected...........

you have chosen such a device which is not large enough to implement the hardware your code is going to generate. You will need to either try to optimize your code, your layout, or move to a larger device. .............

or chose another device which hav e much larger capacity then this device......

If FPGA is overloaded ,then u canot do the Place n Route ,Mapping ,that to u cannot generate .bit map file..............

only u can check the hardware...........

the code is not get doen loaded........

I came to know that number of dsp's make difference whether the fpga is overloaded or not..
and one more thing....
1. is it true that bit file will be generated even when number of slices is just more than 100 i.e is 102%.??

No. If the usage of any resource is >100% at the PAR stage, a correct bit file cannot be created by any means. You cannot use a component that does not exist.

If you are using memory, just check that the memory is sitting in CLB or memory blocks. If the memory consuming CLBs change the coding style of the memory to move it to memory blocks.

I did not get you.please can you elaborate..

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