What happens when concat STD_LOGIC into STD_LOGIC_VECTOR

[legendbb]

Let's say I have 32 independent STD_LOGIC signal each transits on independent logics.

Just being lazy about output port, if I concatenate them into a STD_LOGIC_VECTOR(31 DOWNTO 0). What the impact of this assignment would have for FPGA implementation?

Would this end up with less resource usage or potential timing routing issue?

I assume if I don't register this STD_LOGIC_VECTOR, tool will take it as nets; if I register this signal, logic is different.

Please comment,

Thanks,

 

[SynthWorks]

Concatenation is just bundling of signals (hence think wires) and should not increase or decrease the amount of logic required by the rest of the circuit.

 

[legendbb]

Concatenation is just bundling of signals (hence think wires) and should not increase or decrease the amount of logic required by the rest of the circuit.

Thanks a lot for your reply.