clock jitter?
for example. clock to data skew, is the arrival time difference, between the clock signal, and the data signal, from the uP to the memory. you should to control this, in layout design or floorplanning. it shouldn't be too much. there are thresholds.
maybe the memory gets the clock rising edge, and the it thinks, that it can sample the data lines. but the data lines aren't reade in that time moment, because of the skew.
normal clock skew, as i know, is the arrival difference of the same clock signal, to the different memory modules. in synchron systems (sdram) you should to hold this difference between thresholds.
pin skew: some processors doesn't like that they get a far-non-50% clk signal. maybe because of internal pipelining, or multiphase processing.
see memory/processor datasheets, memory bus specifications...
agilent has wery helpful papers about that. and the fairchild's backplane design guide is also helpful.
you should do timing analyses, to inspect them, and should control them in design stage.
these things are depending on noise, pcb line length, earlier databits(isi), unbalanced load of clock lines ...
maybe i wrote incorrect things?